
 ;  SNES.txt
 ;  
 ;  Written by illegal eagle for vSNES 2.86; last update: 2006-03-17 18:30
 ;  Feel free to use this info for anything you want, but don't expect it to be perfect.
 ;  Use no line-wrap and a tabulator width of 8 chars (as in Notepad) for viewing.

 ;  The registers are sorted by index and are grouped by function.
 ;  The 1st column contains the address of the registers.
 ;  The 2nd column contains the type:
 ;
 ;	"RWxVHFA":	'R' = a meaningful value can be read from the register
 ;			'W' = the register accepts values via write accesses
 ;			'x':	'1' = the value is in one byte	("byte value"),
 ;				'2' = the value is in two bytes	("word value"), ...
 ;				'L' = the value is the  low byte of a larger internal value
 ;				'M' = the value is the  2nd byte of a larger internal value
 ;				'H' = the value is the high byte of a larger internal value
 ;			'V' = the register can be accessed during V-Blank
 ;			'H' = the register can be accessed during H-Blank
 ;			'F' = the register can be accessed during F-Blank (forced blanking)
 ;			'A' = the register can be accessed at any time
 ;
 ;  The 3rd column contains the number of bits.
 ;  The 4th column contains the names of the registers; most docs use a slightly different set.
 ;  The 5th column contains comments to the registers; bits are in reverse order and are named
 ;  D63..D0. These comments are just a short reference and not a full technical doc.

 ;  The write-only registers (or data ports) don't show the value you would get by
 ;  reading, but show the internal status (or the next value to read/overwrite).
 ;
 ;  If an internal register is formed by several normal registers then it's displayed first.
 ;
 ;  Some registers, eg. the DSP registers, are stored in normal RAM.  Therefore they're
 ;  always readable and writeable, but their value is supposed to be set by the hardware.



[CPU]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
							; [5A22 REGISTERS]
		16	C				; Accumulator (B SHL 8 plus A)
		 8	A				; accumulator (low)
		 8	B				; accumulator (high)
		16	X				; index or general purpose register
		16	Y				; index or general purpose register
		 8	P				; NVMXDIZC or NV1BDIZC bits (Processor Status flags)
		24	DBptr				; Data Bank pointer (24-bit effective data address)
		16	D				; Direct Page pointer (Direct Page address in bank 0)
		16	S				; Stack Pointer (stack address in bank 0 if E=0, else bank 1)
		24	PBPC				; effective Program address (PB SHL 16 plus PC)
		 8	PB				; Program Bank
		16	PC				; Program Counter
		 8	DB				; Data Bank (bits 23..16 of the 24-bit effective Data address)

							; [PROCESSOR STATUS FLAGS]
		 1	C				; Carry
		 1	Z				; Result Zero
		 1	I				; IRQ Disable
		 1	D				; Decimal Mode (1) or binary mode (0)
		 1	X				; Index registers: 8-bit (1) or 16-bit (0)
		 1	M				; Memory/Accumulator: 8-bit (1) or 16 bit (0)
		 1	V				; Overflow
		 1	N				; Negative
		 1	E				; 6502 Emulation (hidden, can be exchanged with C)
		 1	B				; BRK (hidden if E=0, replaces X while E=1)


							; [5A22 STATUS]
		 1	in_INT				; in INT = 1, else 0
		 1	in_NMI				; in NMI = 1, else 0
		 8	Cycles_Line			; cycles per scanline
		 8	Cycles_LineLeft			; cycles left in scanline
		 8	Cycles_HBLANK			; cycles per hblank


							; [MEMORY-MAPPED REGISTERS]
 4016	RW1VHFA	 2	JoySer0				; famicom-style data port for ctrl 1 and 3
 4017	R?1VHFA	 2	JoySer1				; famicom-style data port for ctrl 2 and 4 (D4..D2 are always set)

 4200	_W1VHF?	 8	NMITimEn			; enable NMI (D7); check y-pos (D5) and/or x-pos (D4) to generate IRQ; Auto-Joypad Read (D0)
 4201	_W1VHFA	 8	wrIO				; programmable I/O port (OUT port)
 4202	_W1VHFA	 8	wrMpyA				; multiplier
 4203	_W1VHFA	 8	wrMpyB				; multiplicant
	_W2VHFA	16	wrDiv				; divident
 4204	_WLVHFA	 8	wrDivL				; divident (low)
 4205	_WHVHFA	 8	wrDivH				; divident (high)
 4206	_W1VHFA	 8	wrDivB				; divisor
	_W2VHFA	 9	hTime				; x-pos. for IRQ check
 4207	_WLVHFA	 8	hTimeL				; x-pos. for IRQ check (bits 7..0)
 4208	_WHVHFA	 1	hTimeH				; x-pos. for IRQ check (bit 8)
	_W2VHFA	 9	vTime				; y-pos. for IRQ check
 4209	_WLVHFA	 8	vTimeL				; y-pos. for IRQ check (bits 7..0)
 420A	_WHVHFA	 1	vTimeH				; y-pos. for IRQ check (bit 8)
 420B	_W1VHFA	 8	mDMAEn				; status flags: DMA channels
 420C	_W1VHFA	 8	hDMAEn				; status flags: HDMA channels
 420D	_W1VHFA	 1	MemSel				; cart ROM speed at 80:8000 and above: 6 (D0=1) or 8 (D0=0) master cycles

 4210	R_1VHFA	 8	rdNMI				; NMI flag by V-Blank (D7) (reset by read), 5A22 version (D3..D0)
 4211	R_1VHFA	 8	TimeUp				; 'H-IRQ or V-IRQ' flag (D7); becomes zero after reading
 4212	R_1VHFA	 8	HVBJoy				; V-Blank (D7), H-Blank (D6), JOY Reading (D0)
 4213	R_1VHFA	 8	rdIO				; programmable I/O port (IN port)
	R_2VHFA	16	rdDiv				; quotient of divide result
 4214	R_LVHFA	 8	rdDivL				; quotient of divide result (low)
 4215	R_HVHFA	 8	rdDivH				; quotient of divide result (high)
	R_2VHFA	16	rdMpy				; product of mult. result or remainder of div. result
 4216	R_LVHFA	 8	rdMpyL				; product of mult. result or remainder of div. result (low)
 4217	R_HVHFA	 8	rdMpyH				; product of mult. result or remainder of div. result (high)

 4218	R_1VHFA	 8	Joy1L				; JOY ctrl 1 (D7..D4): X, Y, Top Right, Top Left
 4219	R_1VHFA	 8	Joy1H				; JOY ctrl 1 (D7..D0): A, B, Select, Start, Up, Down, Left, Right
 421A	R_1VHFA	 8	Joy2L				; JOY ctrl 2 (D7..D4): X, Y, Top Right, Top Left
 421B	R_1VHFA	 8	Joy2H				; JOY ctrl 2 (D7..D0): A, B, Select, Start, Up, Down, Left, Right
 421C	R_1VHFA	 8	Joy3L				; JOY ctrl 3 (D7..D4): X, Y, Top Right, Top Left
 421D	R_1VHFA	 8	Joy3H				; JOY ctrl 3 (D7..D0): A, B, Select, Start, Up, Down, Left, Right
 421E	R_1VHFA	 8	Joy4L				; JOY ctrl 4 (D7..D4): X, Y, Top Right, Top Left
 421F	R_1VHFA	 8	Joy4H				; JOY ctrl 4 (D7..D0): A, B, Select, Start, Up, Down, Left, Right



[DMA]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 420B	_W1VHFA	 8	mDMAEn				; status flags: DMA channels
 420C	_W1VHFA	 8	hDMAEn				; status flags: HDMA channels

							; [INFO FOR CHANNELS 0..7]
 4300	RW1VHFA	 8	dma0Param			; DMA & HDMA transfer parameters
 4310	RW1VHFA	 8	dma1Param			; (A-Bus = CART & WRAM; B-Bus = PPU, APU & WRAM)
 4320	RW1VHFA	 8	dma2Param
 4330	RW1VHFA	 8	dma3Param			; D7 = Bus transfer direction: B to A (1) or A to B (0)
 4340	RW1VHFA	 8	dma4Param			; D6 = HDMA addressing mode: indirect (1) or direct (0)
 4350	RW1VHFA	 8	dma5Param			; D4 = inc/dec setting for D3=0: automatic dec. (1) or inc. (0)
 4360	RW1VHFA	 8	dma6Param			; D3 = DMA start address: fixed (1) or automatic inc/dec (0)
 4370	RW1VHFA	 8	dma7Param			; D2..D0 = DMA & HDMA transfer mode

 4301	RW1VHFA	 8	dma0B				; B-Bus address
 4311	RW1VHFA	 8	dma1B				; address of the register will be 21??h
 4321	RW1VHFA	 8	dma2B
 4331	RW1VHFA	 8	dma3B
 4341	RW1VHFA	 8	dma4B
 4351	RW1VHFA	 8	dma5B
 4361	RW1VHFA	 8	dma6B
 4371	RW1VHFA	 8	dma7B

	RW2VHFA	16	dma0A1				; DMA start address / HDMA table address
	RW2VHFA	16	dma1A1
	RW2VHFA	16	dma2A1
	RW2VHFA	16	dma3A1
	RW2VHFA	16	dma4A1
	RW2VHFA	16	dma5A1
	RW2VHFA	16	dma6A1
	RW2VHFA	16	dma7A1

 4302	RWLVHFA	 8	dma0A1L				; DMA start address / HDMA table address
 4312	RWLVHFA	 8	dma1A1L				; (low byte)
 4322	RWLVHFA	 8	dma2A1L
 4332	RWLVHFA	 8	dma3A1L
 4342	RWLVHFA	 8	dma4A1L
 4352	RWLVHFA	 8	dma5A1L
 4362	RWLVHFA	 8	dma6A1L
 4372	RWLVHFA	 8	dma7A1L

 4303	RWHVHFA	 8	dma0A1H				; DMA start address / HDMA table address
 4313	RWHVHFA	 8	dma1A1H				; (high byte)
 4323	RWHVHFA	 8	dma2A1H
 4333	RWHVHFA	 8	dma3A1H
 4343	RWHVHFA	 8	dma4A1H
 4353	RWHVHFA	 8	dma5A1H
 4363	RWHVHFA	 8	dma6A1H
 4373	RWHVHFA	 8	dma7A1H

 4304	RW1VHFA	 8	dma0ABank			; DMA transfer bank / HDMA table bank
 4314	RW1VHFA	 8	dma1ABank
 4324	RW1VHFA	 8	dma2ABank
 4334	RW1VHFA	 8	dma3ABank
 4344	RW1VHFA	 8	dma4ABank
 4354	RW1VHFA	 8	dma5ABank
 4364	RW1VHFA	 8	dma6ABank
 4374	RW1VHFA	 8	dma7ABank

	RW2VHFA	16	dma0Data			; DMA byte count / indirect HDMA data address
	RW2VHFA	16	dma1Data
	RW2VHFA	16	dma2Data
	RW2VHFA	16	dma3Data
	RW2VHFA	16	dma4Data
	RW2VHFA	16	dma5Data
	RW2VHFA	16	dma6Data
	RW2VHFA	16	dma7Data

 4305	RWLVHFA	 8	dma0DataL			; DMA byte count / indirect HDMA data address
 4315	RWLVHFA	 8	dma1DataL			; (low byte)
 4325	RWLVHFA	 8	dma2DataL
 4335	RWLVHFA	 8	dma3DataL
 4345	RWLVHFA	 8	dma4DataL
 4355	RWLVHFA	 8	dma5DataL
 4365	RWLVHFA	 8	dma6DataL
 4375	RWLVHFA	 8	dma7DataL

 4306	RWHVHFA	 8	dma0DataH			; DMA byte count / indirect HDMA data address
 4316	RWHVHFA	 8	dma1DataH			; (high byte)
 4326	RWHVHFA	 8	dma2DataH
 4336	RWHVHFA	 8	dma3DataH
 4346	RWHVHFA	 8	dma4DataH
 4356	RWHVHFA	 8	dma5DataH
 4366	RWHVHFA	 8	dma6DataH
 4376	RWHVHFA	 8	dma7DataH

 4307	RW1VHFA	 8	dma0HBank			; indirect HDMA data bank
 4317	RW1VHFA	 8	dma1HBank
 4327	RW1VHFA	 8	dma2HBank
 4337	RW1VHFA	 8	dma3HBank
 4347	RW1VHFA	 8	dma4HBank
 4357	RW1VHFA	 8	dma5HBank
 4367	RW1VHFA	 8	dma6HBank
 4377	RW1VHFA	 8	dma7HBank

	RW2VHFA	16	dma0A2				; DMA destination address
	RW2VHFA	16	dma1A2
	RW2VHFA	16	dma2A2
	RW2VHFA	16	dma3A2
	RW2VHFA	16	dma4A2
	RW2VHFA	16	dma5A2
	RW2VHFA	16	dma6A2
	RW2VHFA	16	dma7A2

 4308	RWLVHFA	 8	dma0A2L				; DMA destination address
 4318	RWLVHFA	 8	dma1A2L				; (low byte)
 4328	RWLVHFA	 8	dma2A2L
 4338	RWLVHFA	 8	dma3A2L
 4348	RWLVHFA	 8	dma4A2L
 4358	RWLVHFA	 8	dma5A2L
 4368	RWLVHFA	 8	dma6A2L
 4378	RWLVHFA	 8	dma7A2L

 4309	RWHVHFA	 8	dma0A2H				; DMA destination address
 4319	RWHVHFA	 8	dma1A2H				; (high byte)
 4329	RWHVHFA	 8	dma2A2H
 4339	RWHVHFA	 8	dma3A2H
 4349	RWHVHFA	 8	dma4A2H
 4359	RWHVHFA	 8	dma5A2H
 4369	RWHVHFA	 8	dma6A2H
 4379	RWHVHFA	 8	dma7A2H

 430A	RW1VHFA	 8	dma0HLine			; HDMA Line Counter
 431A	RW1VHFA	 8	dma1HLine			; Repeat (D7), value (D6..D0)
 432A	RW1VHFA	 8	dma2HLine
 433A	RW1VHFA	 8	dma3HLine
 434A	RW1VHFA	 8	dma4HLine
 435A	RW1VHFA	 8	dma5HLine
 436A	RW1VHFA	 8	dma6HLine
 437A	RW1VHFA	 8	dma7HLine



[PPU]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 2100	_W1VHFA	 8	IniDisp				; forced blanking (D7), screen brightness (D3..D0)

 2101	_W1V?F_	 8	OBJSel				; OBJ size (D7..D5), OBJ name (D4..D3), OBJ name base (D1..D0)
	_W2V?F_	 9	OAMAdd				; OAM address
 2102	_WLV?F_	 8	OAMAddL				; OAM address (bits 7..0)
 2103	_WHV?F_	 8	OAMAddH				; OAM priority rotation (D7), bit 8 of OAM address (D0)
 2104	_W1V?F_	 8	OAMData				; data port for writing into OAM

 2105	_W1VHF_	 8	BGMode				; BG4..BG1 char size (D7..D4), BG3-p1 on top (D3), BG mode (D2..D0)
 2106	_W?VHF_	 8	Mosaic				; mosaic size (D7..D4), BG4..BG1 flags (D3..D0)
 2107	_W1V?F_	 7	BG1SC				; BG1 tilemap: address (D6..D2), yres=64 (D1), xres=64 (D0)
 2108	_W1V?F_	 7	BG2SC				; BG2 tilemap: address (D6..D2), yres=64 (D1), xres=64 (D0)
 2109	_W1V?F_	 7	BG3SC				; BG3 tilemap: address (D6..D2), yres=64 (D1), xres=64 (D0)
 210A	_W1V?F_	 7	BG4SC				; BG4 tilemap: address (D6..D2), yres=64 (D1), xres=64 (D0)
 210B	_W1V?F_	 8	BG12NBA				; name base address: BG2 (D7..D4), BG1 (D3..D0)
 210C	_W1V?F_	 8	BG34NBA				; name base address: BG4 (D7..D4), BG3 (D3..D0)
 210D	_W2VHF_	13	BG1hOfs				; BG1 H-Offset (D9..D0; D12..D0 in Mode7)
 210E	_W2VHF_	13	BG1vOfs				; BG1 V-Offset (D9..D0; D12..D0 in Mode7)
 210F	_W2VHF_	10	BG2hOfs				; BG2 H-Offset (D9..D0)
 2110	_W2VHF_	10	BG2vOfs				; BG2 V-Offset (D9..D0)
 2111	_W2VHF_	10	BG3hOfs				; BG3 H-Offset (D9..D0)
 2112	_W2VHF_	10	BG3vOfs				; BG3 V-Offset (D9..D0)
 2113	_W2VHF_	10	BG4hOfs				; BG4 H-Offset (D9..D0)
 2114	_W2VHF_	10	BG4vOfs				; BG4 V-Offset (D9..D0)

 2115	_W1V?F_	 8	VMAInc				; incr. at 2118h/2139h or 2119h/213Ah access (D7), sequence mode (D3..D0)
	_W2V?F_	16	VMAddB				; VRAM address; points to a VRAM byte
	_W2V?F_	15	VMAdd				; VRAM address; points to a VRAM word
 2116	_WLV?F_	 8	VMAddL				; VRAM address (bits 7..0)
 2117	_WHV?F_	 7	VMAddH				; VRAM address (bits 14..8)
	_W2V_F_	16	VMData				; data port for writing into VRAM
 2118	_WLV_F_	 8	VMDataL				; data port for writing into VRAM (low)
 2119	_WHV_F_	 8	VMDataH				; data port for writing into VRAM (high)

 211A	_W1V?F_	 8	M7Sel				; screen over setting (D7..D6), screen flip (D1..D0)
 211B	_W2VHF_	16	M7A				; matrix parameter A (D15..D0)
 211C	_W2VHF_	16	M7B				; matrix parameter B (D15..D0)
 211D	_W2VHF_	16	M7C				; matrix parameter C (D15..D0)
 211E	_W2VHF_	16	M7D				; matrix parameter D (D15..D0)
 211F	_W2VHF_	13	M7X				; center: x position (D12..D0)
 2120	_W2VHF_	13	M7Y				; center: y position (D12..D0)

	_W1VHF_	 9	CGAddB				; CGRAM address; points to CGRAM byte
 2121	_W1VHF_	 8	CGAdd				; CGRAM address; points to CGRAM word (palette entry)
 2122	_W2VHF_	15	CGDataW				; data port for writing into CGRAM (D14..D0)

 2123	_W1VHF_	 8	W12Sel				; wnd2 on,inv, wnd1 on,inv: BG2 (D7..D4), BG1 (D3..D0)
 2124	_W1VHF_	 8	W34Sel				; wnd2 on,inv, wnd1 on,inv: BG4 (D7..D4), BG3 (D3..D0)
 2125	_W1VHF_	 8	WOBJSel				; wnd2 on,inv, wnd1 on,inv: color window (D7..D4), OBJ (D3..D0)
 2126	_W1VHF_	 8	WH0				; window 1: first pixel (left position)
 2127	_W1VHF_	 8	WH1				; window 1: last pixel (right position)
 2128	_W1VHF_	 8	WH2				; window 2: first pixel (left position)
 2129	_W1VHF_	 8	WH3				; window 2: last pixel (right position)
 212A	_W1VHF_	 8	WBGLog				; 0..3=OR/AND/XOR/XNOR: BG4..BG1 (D7..D0, 2 bits each)
 212B	_W1VHF_	 4	WOBJLog				; 0..3=OR/AND/XOR/XNOR: color window (D3..D2), OBJ (D1..D0)
 212C	_W1VHF_	 5	TM				; OBJ (D4), BG4..BG1 (D3..D0): designation for main screen
 212D	_W1VHF_	 5	TS				; OBJ (D4), BG4..BG1 (D3..D0): designation for sub screen
 212E	_W1VHF_	 5	TMW				; OBJ (D4), BG4..BG1 (D3..D0): mask window on main screen
 212F	_W1VHF_	 5	TSW				; OBJ (D4), BG4..BG1 (D3..D0): mask window on sub screen

 2130	_W1VHF_	 8	CGSWSel				; 0..3=off/out/in/all: clip to black (D7..D6), no math (D5..D4); use SubScr. (D1), direct col. (D0)
 2131	_W1VHF_	 8	CGAdSub				; add/sub mode (D7), 0.5 mode (D6); D5..D0: add/sub on BACK, OBJ, BG4..BG1
 2132	_W1VHF_	15	ColData				; color constant
	_W1VHF_	 5	ColRed				; color constant: red
	_W1VHF_	 5	ColGreen			; color constant: green
	_W1VHF_	 5	ColBlue				; color constant: blue
 2133	_W1VHF_	 8	SetIni				; ext. sync (D7), EXTBG (D6), H-512 (D3), V-239 (D2), OBJ-V x1 (D1), interlace (D0)

	R_3VHF?	24	Mpy				; multiplication result
 2134	R_LVHF?	 8	MpyL				; multiplication result (low)
 2135	R_MVHF?	 8	MpyM				; multiplication result (mid)
 2136	R_HVHF?	 8	MpyH				; multiplication result (high)

 2137	R_0VHFA	 8	SLHV				; read access latches H/V-Counter, returned data is Open Bus
 2138	R_2V?F_	 8	OAMData				; data port for reading from OAM
	R_2V?F_	16	VMData				; data port for reading from VRAM
 2139	R_LV?F_	 8	VMDataL				; data port for reading from VRAM (low)
 213A	R_HV?F_	 8	VMDataH				; data port for reading from VRAM (high)
 213B	R_2V?F_	 8	CGDataR				; data port for reading from CGRAM (two reads; bit 15 is PPU2 Open Bus)
 213C	R_2VHFA	 9	OPhCt				; output data of H-Counter; visible area = 22..277
 213D	R_2VHFA	 9	OPvCt				; output data of V-Counter; visible area = 1..224 or 1..239(?)
 213E	R_1VHFA	 8	Stat77				; Time Over (D7), Range Over (D6), master/slave (D5), 5C77 version (D3..D0)
 213F	R_1VHFA	 8	Stat78				; field (D7), external latch (D6), PAL mode (D4), 5C78 version (D3..D0)

 2140	RW1VHFA	 8	APUIO0				; APU I/O port 0 data that the SPC700 wrote to 00F4h
 2141	RW1VHFA	 8	APUIO1				; APU I/O port 1 data that the SPC700 wrote to 00F5h
 2142	RW1VHFA	 8	APUIO2				; APU I/O port 2 data that the SPC700 wrote to 00F6h
 2143	RW1VHFA	 8	APUIO3				; APU I/O port 3 data that the SPC700 wrote to 00F7h
							; (APU I/O ports are mirrored up to 217C..217F)

 2180	RW1VHFA	 8	WMData				; data port for reading from WRAM and writing into WRAM
	_W3VHFA	17	WMAdd				; WRAM (RAM) address
 2181	_W1VHFA	 8	WMAddL				; WRAM (RAM) address (bits 7..0)
 2182	_W1VHFA	 8	WMAddM				; WRAM (RAM) address (bits 15..8)
 2183	_W1VHFA	 1	WMAddH				; WRAM (RAM) address (bit 16)



[APU]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
							; [SONY-SPC700 REGISTERS]
		16	YA				; Accumulator (Y SHL 8 plus A)
		 8	A				; accumulator (low)
		 8	X				; index or general purpose register
		 8	Y				; index or general purpose register / accumulator (high)
		 8	PSW				; NVP-H-ZC bits (Processor Status Ward flags)
		16	PC				; Program Counter (PCH SHL 8 plus PCL)
		 8	PCL				; program counter (low)
		 8	PCH				; program counter (high)
		 8	DP				; Direct Page pointer
		 8	SP				; Stack Pointer (effective address = 0100h + SP)

							; [PROCESSOR STATUS FLAGS]
		 1	C				; Carry
		 1	Z				; Zero
		 1	H				; Half Carry
		 1	D				; Direct Page; Direct Page address = 0000h (0) or 0100h (1)
		 1	V				; Overflow
		 1	N				; Negative

 00F0	RW?	 8	spcTest				; SPC700 speed (D7..D4), lock CPU (D2), enable RAM writes (D1); timers need D3=1 and D0=0
 00F1	RW?	 6	spcCtrl				; show ROM at FFC0h (D7), I/O port clear bits (D5..D4), timer status (D2..D0)
 00F2	RW?	 8	spcDRgA				; DSP register address
 00F3	RW?	 8	spcDDat				; port for reading and writing DSP register data

 00F4	RW?	 8	spcPort0			; APU I/O port 0 data that the 5A22 wrote to 2140h
 00F5	RW?	 8	spcPort1			; APU I/O port 1 data that the 5A22 wrote to 2141h
 00F6	RW?	 8	spcPort2			; APU I/O port 2 data that the 5A22 wrote to 2142h
 00F7	RW?	 8	spcPort3			; APU I/O port 3 data that the 5A22 wrote to 2143h

 00FA	RW?	 8	spcTmLt0			; latch (hit value) for timer0 (8 kHz)
 00FB	RW?	 8	spcTmLt1			; latch (hit value) for timer1 (8 kHz)
 00FC	RW?	 8	spcTmLt2			; latch (hit value) for timer2 (64 kHz)
 00FD	RW?	 4	spcTmCt0			; timer0 hit counter (D3..D0); used bits get cleared by reading
 00FE	RW?	 4	spcTmCt1			; timer1 hit counter (D3..D0); used bits get cleared by reading
 00FF	RW?	 4	spcTmCt2			; timer2 hit counter (D3..D0); used bits get cleared by reading


							; [SONY-DSP (SFC APU) REGISTERS]
 000C	RW?	 8	MVolumeL			; master volume: sign (D7), value (D6..D0) for left
 001C	RW?	 8	MVolumeR			; master volume: sign (D7), value (D6..D0) for right
 002C	RW?	 8	EVolumeL			; echo volume: sign (D7), value (D6..D0) for left
 003C	RW?	 8	EVolumeR			; echo volume: sign (D7), value (D6..D0) for right
 004C	RW?	 8	KeyOn				; voice flags: key-on
 005C	RW?	 8	KeyOff				; voice flags: key-off
 006C	RW?	 8	FLG				; reset (D7), mute (D6), echo buffer lock (D5), noise clock (D4..D0)
 007C	RW?	 8	EndX				; voice flags: source end block encountered; write access clears all bits

 000D	RW?	 8	EchoFB				; echo feedback: sign (D7), value (D6..D0)
 002D	RW?	 8	PitchMod			; voice flags: pitch modulation  (D7..D1)
 003D	RW?	 8	NoiseON				; voice flags: noise
 004D	RW?	 8	EchoON				; voice flags: echo
 005D	RW?	 8	DIR				; high byte of the sample directory address; low byte is always 0
 006D	RW?	 8	EchoSAddr			; high byte of the echo ring buffer directory address; low byte is always 0
 007D	RW?	 4	EchoDelay			; echo delay (ring buffer size)

 000F	RW?	 8	C0				; echo FIR filter coefficients
 001F	RW?	 8	C1				; sign (D7), value (D6..D0)
 002F	RW?	 8	C2
 003F	RW?	 8	C3
 004F	RW?	 8	C4
 005F	RW?	 8	C5
 006F	RW?	 8	C6
 007F	RW?	 8	C7

							; [INFO FOR DSP VOICES 0..7]
 0000	RW?	 8	V0VolumeL			; volume for left
 0010	RW?	 8	V1VolumeL			; sign (D7), value (D6..D0)
 0020	RW?	 8	V2VolumeL
 0030	RW?	 8	V3VolumeL
 0040	RW?	 8	V4VolumeL
 0050	RW?	 8	V5VolumeL
 0060	RW?	 8	V6VolumeL
 0070	RW?	 8	V7VolumeL

 0001	RW?	 8	V0VolumeR			; volume for right
 0011	RW?	 8	V1VolumeR			; sign (D7), value (D6..D0)
 0021	RW?	 8	V2VolumeR
 0031	RW?	 8	V3VolumeR
 0041	RW?	 8	V4VolumeR
 0051	RW?	 8	V5VolumeR
 0061	RW?	 8	V6VolumeR
 0071	RW?	 8	V7VolumeR

	RW?	14	V0Pitch				; pitch scaler
	RW?	14	V1Pitch
	RW?	14	V2Pitch
	RW?	14	V3Pitch
	RW?	14	V4Pitch
	RW?	14	V5Pitch
	RW?	14	V6Pitch
	RW?	14	V7Pitch

 0002	RW?	 8	V0PitchL			; pitch scaler (bits 7..0)
 0012	RW?	 8	V1PitchL
 0022	RW?	 8	V2PitchL
 0032	RW?	 8	V3PitchL
 0042	RW?	 8	V4PitchL
 0052	RW?	 8	V5PitchL
 0062	RW?	 8	V6PitchL
 0072	RW?	 8	V7PitchL

 0003	RW?	 6	V0PitchH			; pitch scaler (bits 13..8)
 0013	RW?	 6	V1PitchH
 0023	RW?	 6	V2PitchH
 0033	RW?	 6	V3PitchH
 0043	RW?	 6	V4PitchH
 0053	RW?	 6	V5PitchH
 0063	RW?	 6	V6PitchH
 0073	RW?	 6	V7PitchH

 0004	RW?	 8	V0SrcN				; source sample number
 0014	RW?	 8	V1SrcN
 0024	RW?	 8	V2SrcN
 0034	RW?	 8	V3SrcN
 0044	RW?	 8	V4SrcN
 0054	RW?	 8	V5SrcN
 0064	RW?	 8	V6SrcN
 0074	RW?	 8	V7SrcN

 0005	RW?	 8	V0ADSR1				; ADSR 1
 0015	RW?	 8	V1ADSR1				; ADSR enabled (D7), DR (D6..D4), AR (D3..D0)
 0025	RW?	 8	V2ADSR1
 0035	RW?	 8	V3ADSR1
 0045	RW?	 8	V4ADSR1
 0055	RW?	 8	V5ADSR1
 0065	RW?	 8	V6ADSR1
 0075	RW?	 8	V7ADSR1

 0006	RW?	 8	V0ADSR2				; ADSR 2
 0016	RW?	 8	V1ADSR2				; SL (D7..D4), SR (D3..D0)
 0026	RW?	 8	V2ADSR2
 0036	RW?	 8	V3ADSR2
 0046	RW?	 8	V4ADSR2
 0056	RW?	 8	V5ADSR2
 0066	RW?	 8	V6ADSR2
 0076	RW?	 8	V7ADSR2

 0007	RW?	 8	V0Gain				; GAIN setting
 0017	RW?	 8	V1Gain				; indirect (D7), inc. (D6), non-linear (D5), value (direct: D6..D0, else D4..D0)
 0027	RW?	 8	V2Gain
 0037	RW?	 8	V3Gain				; 0???????  =  direct designation
 0047	RW?	 8	V4Gain				; 110?????  =  increase mode (linear)
 0057	RW?	 8	V5Gain				; 111?????  =  increase mode (bent line)
 0067	RW?	 8	V6Gain				; 100?????  =  decrease mode (linear)
 0077	RW?	 8	V7Gain				; 101?????  =  decrease mode (exponential)

 0008	RW?	 7	V0EnvX				; current value of the ADSR/Gain envelope constant (D6..D0)
 0018	RW?	 7	V1EnvX				; (content is set by DSP)
 0028	RW?	 7	V2EnvX
 0038	RW?	 7	V3EnvX
 0048	RW?	 7	V4EnvX
 0058	RW?	 7	V5EnvX
 0068	RW?	 7	V6EnvX
 0078	RW?	 7	V7EnvX

 0009	RW?	 8	V0OutX				; current value after envelope multiplication (current wave height value)
 0019	RW?	 8	V1OutX				; (content is set by DSP)
 0029	RW?	 8	V2OutX				; sign (D7), value (D6..D0)
 0039	RW?	 8	V3OutX
 0049	RW?	 8	V4OutX
 0059	RW?	 8	V5OutX
 0069	RW?	 8	V6OutX
 0079	RW?	 8	V7OutX



[ZST]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		 8	versn				; version #/100
		 8	curcyc				; cycles left in scanline
		16	curypos				; current y position
		 8	cacheud				; update cache every ? frames
		 8	ccud				; current cache increment
		 8	intrset				; interrupt set
		 8	cycpl				; cycles per scanline
		 8	cycphb				; cycles per hblank
		 8	spcon				; SPC Enable (1=enabled)
		16	stackand			; value to and stack to keep it from going to the wrong area
		16	stackor				; value to or stack to keep it from going to the wrong area

							; [65816 registers]
		16	xat
		 8	xdbt
		 8	xpbt
		16	xst
		16	xdt
		16	xxt
		16	xyt
		 8	xp
		 8	xe
		16	xpc
		 8	xirqb				; which bank the irqs start at
		 8	debugger			; Start with debugger (1=yes, 0=no)
		32	Curtableaddr			; Current table address
		 8	curnmi				; if in NMI (1) or not (0)
		32	cycpbl				; percentage left of CPU/SPC to run  (3.58 = 175)
		32	cycpblt				; percentage of CPU/SPC to run

							; [SNES PPU Registers]
		 8	sndrot				; rotates to use A,X or Y for sound skip
		 8	sndrot2				; rotates a random value for sound skip
		 8	INTEnab				; enables NMI (7) / VIRQ (5) / HIRQ (4) / JOY (0)
		 8	NMIEnab				; controlled in e65816 loop.  Sets to 81h
		16	VIRQLoc				; VIRQ Y location
		 8	vidbright			; screen brightness (0..15)
		 8	previdbr			; previous screen brightness
		 8	forceblnk			; force blanking on/off (80h=on)
		32	objptr				; pointer to object data in VRAM
		32	objptrn				; pointer2 to object data in VRAM
		 8	objsize1			; 1 = 8dot, 4=16 dot, 16=32 dot, 64=64 dot
		 8	objsize2			; large object size
		 8	objmovs1			; number of bytes to move/paragraph
		16	objadds1			; number of bytes to add/paragraph
		 8	objmovs2			; number of bytes to move/paragraph
		16	objadds2			; number of bytes to add/paragraph
		16	oamaddrt			; oam address
		16	oamaddrs			; oam address at beginning of vblank
		 8	objhipr				; highest priority object #
		 8	bgmode				; graphics mode (0..7)
		 8	bg3highst			; is 1 if background 3 has the highest priority
		 8	bgtilesz			; 0=8x8, 1=16x16; bit0=bg1, bit1=bg2, etc
		 8	mosaicon			; mosaic on, bit 0=bg1, bit1=bg2, etc
		 8	mosaicsz			; mosaic size in pixels
		16	bg1ptr				; pointer to background1
		16	bg2ptr				; pointer to background2
		16	bg3ptr				; pointer to background3
		16	bg4ptr				; pointer to background4
		16	bg1ptrb				; pointer to background1
		16	bg2ptrb				; pointer to background2
		16	bg3ptrb				; pointer to background3
		16	bg4ptrb				; pointer to background4
		16	bg1ptrc				; pointer to background1
		16	bg2ptrc				; pointer to background2
		16	bg3ptrc				; pointer to background3
		16	bg4ptrc				; pointer to background4
		16	bg1ptrd				; pointer to background1
		16	bg2ptrd				; pointer to background2
		16	bg3ptrd				; pointer to background3
		16	bg4ptrd				; pointer to background4
		 8	bg1scsize			; bg #1 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		 8	bg2scsize			; bg #2 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		 8	bg3scsize			; bg #3 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		 8	bg4scsize			; bg #4 screen size (0=1x1, 1=1x2, 2=2x1, 3=2x2)
		16	bg1objptr			; pointer to tiles in background1
		16	bg2objptr			; pointer to tiles in background2
		16	bg3objptr			; pointer to tiles in background3
		16	bg4objptr			; pointer to tiles in background4
		16	bg1scrolx			; background 1 x position
		16	bg2scrolx			; background 2 x position
		16	bg3scrolx			; background 3 x position
		16	bg4scrolx			; background 4 x position
		16	bg1sx				; Temporary Variable for Debugging purposes
		16	bg1scroly			; background 1 y position
		16	bg2scroly			; background 2 y position
		16	bg3scroly			; background 3 y position
		16	bg4scroly			; background 4 y position
		16	addrincr			; vram increment (2, 64, 128, 256)
		 8	vramincr			; 0 = inrement at 2118/2139, 1 = 2119,213A
		 8	vramread			; 0 = address set, 1 = already read once
		32	vramaddr			; vram address
		16	cgaddr				; cg (palette) address
		 8	cgmod				; if cgram is modified or not
		16	scrnon				; main & sub screen on
		 8	scrndist			; which background is disabled
		16	resolutn			; screen resolution
		 8	multa				; multiplier A
		16	diva				; divisor C
		16	divres				; quotent of divc/divb
		16	multres				; result of multa * multb/remainder of divc/divb
		16	latchx				; latched x value
		16	latchy				; latched y value
		 8	latchxr				; low or high byte read for x value
		 8	latchyr				; low or high byte read for y value
		 8	frskipper			; used to control frame skipping
		 8	winl1				; window 1 left position
		 8	winr1				; window 1 right position
		 8	winl2				; window 2 left position
		 8	winr2				; window 2 right position
		 8	winbg1en			; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG1
		 8	winbg2en			; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG2
		 8	winbg3en			; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG3
		 8	winbg4en			; Win1 on (IN/OUT) or Win2 on (IN/OUT) on BG4
		 8	winobjen			; Win1 on (IN/OUT) or Win2 on (IN/OUT) on sprites
		 8	wincolen			; Win1 on (IN/OUT) or Win2 on (IN/OUT) on backarea
		 8	winlogica			; Window logic type for BG1 to 4
		 8	winlogicb			; Window logic type for Sprites and Backarea
		 8	winenabm			; Window logic enable for main screen
		 8	winenabs			; Window logic enable for sub screen
		 8	mode7set			; mode 7 settings
		16	mode7A				; A value for Mode 7
		16	mode7B				; B value for Mode 7
		16	mode7C				; C value for Mode 7
		16	mode7D				; D value for Mode 7
		16	mode7X0				; Center X for Mode 7
		16	mode7Y0				; Center Y for Mode 7
		 8	JoyAPos				; Old-Style Joystick Read Position for Joy 1 & 3
		 8	JoyBPos				; Old-Style Joystick Read Position for Joy 2 & 4
		32	compmult			; Complement Multiplication for Mode 7
		 8	joyalt				; temporary joystick alternation

		32	wramrwadr			; continuous read/write to wram address
		 8	irqon				; if IRQ has been called (80h) or not (0)
		 8	nexthdma			; HDMA data to execute once vblank ends
		 8	curhdma				; Currently executed hdma
		 8	hdmatype			; if first time executing hdma or not
		 5	coladdr				; red value of color to add
		 5	coladdg				; green value of color to add
		 5	coladdb				; blue value of color to add
		 8	colnull				; keep this 0 (when accessing colors by dword)
		 8	scaddset			; screen/color constant addition settings
		 8	scaddtype			; which screen to add/sub
		 8	Voice0Disabl2			; Disable Voice 0
		 8	Voice1Disabl2			; Disable Voice 1
		 8	Voice2Disabl2			; Disable Voice 2
		 8	Voice3Disabl2			; Disable Voice 3
		 8	Voice4Disabl2			; Disable Voice 4
		 8	Voice5Disabl2			; Disable Voice 5
		 8	Voice6Disabl2			; Disable Voice 6
		 8	Voice7Disabl2			; Disable Voice 7

		 8	vraminctype

							; [New variables]
		 8	vramincby8on			; if increment by 8 is on
		 8	vramincby8left			; how many left
		 8	vramincby8totl			; how many in total (32, 64, 128)
		 8	vramincby8rowl			; how many left in that row (start at 8)
		16	vramincby8ptri			; increment by how many when rowl = 0

		 8	nexthprior
		 8	doirqnext

		16	vramincby8var
		 8	screstype
		 8	extlatch
		 8	cfield
		 8	interlval

		16	HIRQLoc				; HIRQ X location

		 8	KeyOnStA
		 8	KeyOnStB

		 8	SDD1BankA
		 8	SDD1BankB
		 8	SDD1BankC
		 8	SDD1BankD
		 8	vramread2			; previous character for vram read
		 8	nosprincr
		16	poamaddrs
		 8	ioportval
		 8	iohvlatch
		 8	ppustatus

							; -------------------------------------

							; [SPC700 Status Area]

		32	spcPCRam			; Program Counter
		32	spcA				; The A register (general purpose)
		32	spcX				; The X register (general purpose)
		32	spcY				; The Y register (general purpose)
		32	spcP				; The processor status byte (Removed for each flags); NZ are not always processed...
		32	spcNZ				; The processor NZ flag (little speed up hack :) )

		32	spcS				; The stack pointer (always from 100 to 1FF) (added Ram)
		32	spcRamDP			; The direct page pointer
		32	spcCycle			; The Cycle Counter
		 8	reg1read			; read from 65816
		 8	reg2read			; read from 65816
		 8	reg3read			; read from 65816
		 8	reg4read			; read from 65816
		 8	timeron				; timer0 on
		 8	timincr0			; # of ticks before incrementing
		 8	timincr1			; # of ticks before incrementing
		 8	timincr2			; # of ticks before incrementing
		 8	timinl0				; ticks left before incrementing
		 8	timinl1				; ticks left before incrementing
		 8	timinl2				; ticks left before incrementing
		 8	timrcall			; alternating bit 0 to correctly timer timer1 & 2 to 8000hz

							; [DSP Status area]

		32	BRRPlace0			; Place in the BRRBuffer for Voice 0
		32	BRRTemp0			; Keep this 0
		32	BRRPlace1			; Place in the BRRBuffer for Voice 0
		32	BRRTemp1			; Keep this 0
		32	BRRPlace2			; Place in the BRRBuffer for Voice 0
		32	BRRTemp2			; Keep this 0
		32	BRRPlace3			; Place in the BRRBuffer for Voice 0
		32	BRRTemp3			; Keep this 0
		32	BRRPlace4			; Place in the BRRBuffer for Voice 0
		32	BRRTemp4			; Keep this 0
		32	BRRPlace5			; Place in the BRRBuffer for Voice 0
		32	BRRTemp5			; Keep this 0
		32	BRRPlace6			; Place in the BRRBuffer for Voice 0
		32	BRRTemp6			; Keep this 0
		32	BRRPlace7			; Place in the BRRBuffer for Voice 0
		32	BRRTemp7			; Keep this 0

		32	Voice0Freq			; Frequency of Voice 0 (Delta Freq)
		32	Voice1Freq			; Frequency of Voice 1 (Delta Freq)
		32	Voice2Freq			; Frequency of Voice 2 (Delta Freq)
		32	Voice3Freq			; Frequency of Voice 3 (Delta Freq)
		32	Voice4Freq			; Frequency of Voice 4 (Delta Freq)
		32	Voice5Freq			; Frequency of Voice 5 (Delta Freq)
		32	Voice6Freq			; Frequency of Voice 6 (Delta Freq)
		32	Voice7Freq			; Frequency of Voice 7 (Delta Freq)

		16	Voice0Pitch			; Previous Pitch for Voice 0
		16	Voice1Pitch			; Previous Pitch for Voice 1
		16	Voice2Pitch			; Previous Pitch for Voice 2
		16	Voice3Pitch			; Previous Pitch for Voice 3
		16	Voice4Pitch			; Previous Pitch for Voice 4
		16	Voice5Pitch			; Previous Pitch for Voice 5
		16	Voice6Pitch			; Previous Pitch for Voice 6
		16	Voice7Pitch			; Previous Pitch for Voice 7


		 8	Voice0Status			; 0=Not Playing 1=Playing
		 8	Voice1Status
		 8	Voice2Status
		 8	Voice3Status
		 8	Voice4Status
		 8	Voice5Status
		 8	Voice6Status
		 8	Voice7Status

		32	Voice0Ptr			; Ptr to Next BRR Block to be played
		32	Voice1Ptr
		32	Voice2Ptr
		32	Voice3Ptr
		32	Voice4Ptr
		32	Voice5Ptr
		32	Voice6Ptr
		32	Voice7Ptr
		32	Voice0LoopPtr			; Ptr to Loop BRR Block to be played
		32	Voice1LoopPtr			; Ptr to Loop BRR Block to be played
		32	Voice2LoopPtr			; Ptr to Loop BRR Block to be played
		32	Voice3LoopPtr			; Ptr to Loop BRR Block to be played
		32	Voice4LoopPtr			; Ptr to Loop BRR Block to be played
		32	Voice5LoopPtr			; Ptr to Loop BRR Block to be played
		32	Voice6LoopPtr			; Ptr to Loop BRR Block to be played
		32	Voice7LoopPtr			; Ptr to Loop BRR Block to be played

		32	Voice0BufPtr			; Ptr to Buffer Block to be played
		32	Voice1BufPtr			; Ptr to Buffer Block to be played
		32	Voice2BufPtr			; Ptr to Buffer Block to be played
		32	Voice3BufPtr			; Ptr to Buffer Block to be played
		32	Voice4BufPtr			; Ptr to Buffer Block to be played
		32	Voice5BufPtr			; Ptr to Buffer Block to be played
		32	Voice6BufPtr			; Ptr to Buffer Block to be played
		32	Voice7BufPtr			; Ptr to Buffer Block to be played

		32	SoundCounter			; Counter used for sound generation
		32	SoundCounter2			; Counter used for sound generation
		32	Voice0Prev0
		32	Voice1Prev0
		32	Voice2Prev0
		32	Voice3Prev0
		32	Voice4Prev0
		32	Voice5Prev0
		32	Voice6Prev0
		32	Voice7Prev0
		32	Voice0Prev1
		32	Voice1Prev1
		32	Voice2Prev1
		32	Voice3Prev1
		32	Voice4Prev1
		32	Voice5Prev1
		32	Voice6Prev1
		32	Voice7Prev1

		 8	Voice0Loop
		 8	Voice1Loop
		 8	Voice2Loop
		 8	Voice3Loop
		 8	Voice4Loop
		 8	Voice5Loop
		 8	Voice6Loop
		 8	Voice7Loop

		 8	Voice0End
		 8	Voice1End
		 8	Voice2End
		 8	Voice3End
		 8	Voice4End
		 8	Voice5End
		 8	Voice6End
		 8	Voice7End

		 8	Voice0Noise
		 8	Voice1Noise
		 8	Voice2Noise
		 8	Voice3Noise
		 8	Voice4Noise
		 8	Voice5Noise
		 8	Voice6Noise
		 8	Voice7Noise

		 8	Voice0Volume
		 8	Voice1Volume
		 8	Voice2Volume
		 8	Voice3Volume
		 8	Voice4Volume
		 8	Voice5Volume
		 8	Voice6Volume
		 8	Voice7Volume

		 8	Voice0VolumeR
		 8	Voice1VolumeR
		 8	Voice2VolumeR
		 8	Voice3VolumeR
		 8	Voice4VolumeR
		 8	Voice5VolumeR
		 8	Voice6VolumeR
		 8	Voice7VolumeR

		 8	Voice0VolumeL
		 8	Voice1VolumeL
		 8	Voice2VolumeL
		 8	Voice3VolumeL
		 8	Voice4VolumeL
		 8	Voice5VolumeL
		 8	Voice6VolumeL
		 8	Voice7VolumeL

		 8	Voice0Env
		 8	Voice1Env
		 8	Voice2Env
		 8	Voice3Env
		 8	Voice4Env
		 8	Voice5Env
		 8	Voice6Env
		 8	Voice7Env

		 8	Voice0Out
		 8	Voice1Out
		 8	Voice2Out
		 8	Voice3Out
		 8	Voice4Out
		 8	Voice5Out
		 8	Voice6Out
		 8	Voice7Out

		 8	Voice0State			; 1 Attack, 2 Decrease,3 Sustain, 0 Gain
		 8	Voice1State
		 8	Voice2State
		 8	Voice3State
		 8	Voice4State
		 8	Voice5State
		 8	Voice6State
		 8	Voice7State

		32	Voice0Time
		32	Voice1Time
		32	Voice2Time
		32	Voice3Time
		32	Voice4Time
		32	Voice5Time
		32	Voice6Time
		32	Voice7Time

		32	Voice0Attack
		32	Voice1Attack
		32	Voice2Attack
		32	Voice3Attack
		32	Voice4Attack
		32	Voice5Attack
		32	Voice6Attack
		32	Voice7Attack

		32	Voice0Decay
		32	Voice1Decay
		32	Voice2Decay
		32	Voice3Decay
		32	Voice4Decay
		32	Voice5Decay
		32	Voice6Decay
		32	Voice7Decay

		 8	Voice0SustainL
		 8	Voice1SustainL
		 8	Voice2SustainL
		 8	Voice3SustainL
		 8	Voice4SustainL
		 8	Voice5SustainL
		 8	Voice6SustainL
		 8	Voice7SustainL

		 8	Voice0SustainL2
		 8	Voice1SustainL2
		 8	Voice2SustainL2
		 8	Voice3SustainL2
		 8	Voice4SustainL2
		 8	Voice5SustainL2
		 8	Voice6SustainL2
		 8	Voice7SustainL2

		32	Voice0SustainR
		32	Voice1SustainR
		32	Voice2SustainR
		32	Voice3SustainR
		32	Voice4SustainR
		32	Voice5SustainR
		32	Voice6SustainR
		32	Voice7SustainR

		32	Voice0SustainR2
		32	Voice1SustainR2
		32	Voice2SustainR2
		32	Voice3SustainR2
		32	Voice4SustainR2
		32	Voice5SustainR2
		32	Voice6SustainR2
		32	Voice7SustainR2

		32	Voice0IncNumber
		32	Voice1IncNumber
		32	Voice2IncNumber
		32	Voice3IncNumber
		32	Voice4IncNumber
		32	Voice5IncNumber
		32	Voice6IncNumber
		32	Voice7IncNumber

		32	Voice0SLenNumber
		32	Voice1SLenNumber
		32	Voice2SLenNumber
		32	Voice3SLenNumber
		32	Voice4SLenNumber
		32	Voice5SLenNumber
		32	Voice6SLenNumber
		32	Voice7SLenNumber

		32	Voice0SEndNumber
		32	Voice1SEndNumber
		32	Voice2SEndNumber
		32	Voice3SEndNumber
		32	Voice4SEndNumber
		32	Voice5SEndNumber
		32	Voice6SEndNumber
		32	Voice7SEndNumber

		32	Voice0SEndLNumber
		32	Voice1SEndLNumber
		32	Voice2SEndLNumber
		32	Voice3SEndLNumber
		32	Voice4SEndLNumber
		32	Voice5SEndLNumber
		32	Voice6SEndLNumber
		32	Voice7SEndLNumber

		32	Voice0DecreaseNumber
		32	Voice1DecreaseNumber
		32	Voice2DecreaseNumber
		32	Voice3DecreaseNumber
		32	Voice4DecreaseNumber
		32	Voice5DecreaseNumber
		32	Voice6DecreaseNumber
		32	Voice7DecreaseNumber

		32	Voice0EnvInc
		32	Voice1EnvInc
		32	Voice2EnvInc
		32	Voice3EnvInc
		32	Voice4EnvInc
		32	Voice5EnvInc
		32	Voice6EnvInc
		32	Voice7EnvInc

							; 0 = Direct, 1 = Increase, 2 = Increase2, 3 = Decrease, 4 = Decrease2
		 8	Voice0GainType
		 8	Voice1GainType
		 8	Voice2GainType
		 8	Voice3GainType
		 8	Voice4GainType
		 8	Voice5GainType
		 8	Voice6GainType
		 8	Voice7GainType

		32	Voice0GainTime
		32	Voice1GainTime
		32	Voice2GainTime
		32	Voice3GainTime
		32	Voice4GainTime
		32	Voice5GainTime
		32	Voice6GainTime
		32	Voice7GainTime

		 8	Voice0Starting
		 8	Voice1Starting
		 8	Voice2Starting
		 8	Voice3Starting
		 8	Voice4Starting
		 8	Voice5Starting
		 8	Voice6Starting
		 8	Voice7Starting

		32	Freqdisp
		32	SBRateb

		 8	Voice0Looped
		 8	Voice1Looped
		 8	Voice2Looped
		 8	Voice3Looped
		 8	Voice4Looped
		 8	Voice5Looped
		 8	Voice6Looped
		 8	Voice7Looped



[S9X]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
							; [CPU REGISTERS]
		 8	PB				; Program Bank
		 8	DB				; Data Bank
		16	P				; Processor status flags
		16	A				; Accumulator
		16	D				; Direct Page pointer
		16	S				; Stack pointer
		16	X				; index or general purpose register
		16	Y				; index or general purpose register
		16	PC				; Program Counter


							; [CPU STATUS]
		32	Flags
		 1	BranchSkip
		 1	NMIActive
		 1	IRQActive
		 1	WaitingForInterrupt
		 8	WhichEvent
		32	Cycles
		32	NextEvent
		32	V_Counter
		32	MemSpeed
		32	MemSpeedx2
		32	FastROMSpeed


							; [PPU]
		 8	BGMode
		 8	BG3Priority
		 8	Brightness
		 1	VMA.High
		 8	VMA.Increment
		16	VMA.Address
		16	VMA.Mask1
		16	VMA.FullGraphicCount
		16	VMA.Shift

		16	BG1.SCBase			; SCBase
		16	BG2.SCBase
		16	BG3.SCBase
		16	BG4.SCBase
		16	BG1.VOffset			; VOffset
		16	BG2.VOffset
		16	BG3.VOffset
		16	BG4.VOffset
		16	BG1.HOffset			; HOffset
		16	BG2.HOffset
		16	BG3.HOffset
		16	BG4.HOffset
		 8	BG1.BGSize			; BGSize
		 8	BG2.BGSize
		 8	BG3.BGSize
		 8	BG4.BGSize
		16	BG1.NameBase			; NameBase
		16	BG2.NameBase
		16	BG3.NameBase
		16	BG4.NameBase
		16	BG1.SCSize			; SCSize
		16	BG2.SCSize
		16	BG3.SCSize
		16	BG4.SCSize

		 1	CGFLIP
		 8	FirstSprite
		 8	OAMPriorityRotation
		16	OAMAddr
		 8	OAMFlip
		16	OAMTileAddress
		16	IRQVBeamPos
		16	IRQHBeamPos
		16	VBeamPosLatched
		16	HBeamPosLatched
		 8	HBeamFlip
		 8	VBeamFlip
		 8	HVBeamCounterLatched
		16	MatrixA
		16	MatrixB
		16	MatrixC
		16	MatrixD
		16	CentreX
		16	CentreY
		 8	Joypad1ButtonReadPos
		 8	Joypad2ButtonReadPos
		 8	Joypad3ButtonReadPos
		 8	CGADD
		 8	FixedColourRed
		 8	FixedColourGreen
		 8	FixedColourBlue
		16	SavedOAMAddr
		16	ScreenHeight
		32	WRAM
		 1	ForcedBlanking
		 8	OBJNameSelect
		 8	OBJSizeSelect
		16	OBJNameBase
		 8	OAMReadFlip
		 1	VTimerEnabled
		 1	HTimerEnabled
		16	HTimerPosition
		 8	Mosaic
		 1	Mode7HFlip
		 1	Mode7VFlip
		 8	Mode7Repeat
		 8	Window1Left
		 8	Window1Right
		 8	Window2Left
		 8	Window2Right
		 8	ClipWindowOverlapLogic[0]	; overlap logic
		 8	ClipWindowOverlapLogic[1]
		 8	ClipWindowOverlapLogic[2]
		 8	ClipWindowOverlapLogic[3]
		 8	ClipWindowOverlapLogic[4]
		 8	ClipWindowOverlapLogic[5]
		 1	ClipWindow1Enable[0]		; enable
		 1	ClipWindow1Enable[1]
		 1	ClipWindow1Enable[2]
		 1	ClipWindow1Enable[3]
		 1	ClipWindow1Enable[4]
		 1	ClipWindow1Enable[5]
		 1	ClipWindow2Enable[0]
		 1	ClipWindow2Enable[1]
		 1	ClipWindow2Enable[2]
		 1	ClipWindow2Enable[3]
		 1	ClipWindow2Enable[4]
		 1	ClipWindow2Enable[5]
		 1	ClipWindow1Inside[0]		; inside
		 1	ClipWindow1Inside[1]
		 1	ClipWindow1Inside[2]
		 1	ClipWindow1Inside[3]
		 1	ClipWindow1Inside[4]
		 1	ClipWindow1Inside[5]
		 1	ClipWindow2Inside[0]
		 1	ClipWindow2Inside[1]
		 1	ClipWindow2Inside[2]
		 1	ClipWindow2Inside[3]
		 1	ClipWindow2Inside[4]
		 1	ClipWindow2Inside[5]
		 8	CGFLIPRead
		 1	Need16x8Mulitply
		 1	BGMosaic[0]
		 1	BGMosaic[1]
		 1	BGMosaic[2]
		 1	BGMosaic[3]
		 1	Need16x8Mulitply_2
		 8	MouseSpeed[0]
		 8	MouseSpeed[1]

							; [DMA]
		 1	Chn[0].TransferDirection	; transfer direction
		 1	Chn[1].TransferDirection
		 1	Chn[2].TransferDirection
		 1	Chn[3].TransferDirection
		 1	Chn[4].TransferDirection
		 1	Chn[5].TransferDirection
		 1	Chn[6].TransferDirection
		 1	Chn[7].TransferDirection
		 1	Chn[0].AAddressFixed		; AAddressFixed
		 1	Chn[1].AAddressFixed
		 1	Chn[2].AAddressFixed
		 1	Chn[3].AAddressFixed
		 1	Chn[4].AAddressFixed
		 1	Chn[5].AAddressFixed
		 1	Chn[6].AAddressFixed
		 1	Chn[7].AAddressFixed
		 1	Chn[0].AAddressDecrement	; AAddressDecrement
		 1	Chn[1].AAddressDecrement
		 1	Chn[2].AAddressDecrement
		 1	Chn[3].AAddressDecrement
		 1	Chn[4].AAddressDecrement
		 1	Chn[5].AAddressDecrement
		 1	Chn[6].AAddressDecrement
		 1	Chn[7].AAddressDecrement
		 8	Chn[0].TransferMode		; TransferMode
		 8	Chn[1].TransferMode
		 8	Chn[2].TransferMode
		 8	Chn[3].TransferMode
		 8	Chn[4].TransferMode
		 8	Chn[5].TransferMode
		 8	Chn[6].TransferMode
		 8	Chn[7].TransferMode
		 8	Chn[0].ABank			; ABank
		 8	Chn[1].ABank
		 8	Chn[2].ABank
		 8	Chn[3].ABank
		 8	Chn[4].ABank
		 8	Chn[5].ABank
		 8	Chn[6].ABank
		 8	Chn[7].ABank
		16	Chn[0].AAddress			; AAddress
		16	Chn[1].AAddress
		16	Chn[2].AAddress
		16	Chn[3].AAddress
		16	Chn[4].AAddress
		16	Chn[5].AAddress
		16	Chn[6].AAddress
		16	Chn[7].AAddress
		16	Chn[0].Address			; Address
		16	Chn[1].Address
		16	Chn[2].Address
		16	Chn[3].Address
		16	Chn[4].Address
		16	Chn[5].Address
		16	Chn[6].Address
		16	Chn[7].Address
		 8	Chn[0].BAddress			; BAddress
		 8	Chn[1].BAddress
		 8	Chn[2].BAddress
		 8	Chn[3].BAddress
		 8	Chn[4].BAddress
		 8	Chn[5].BAddress
		 8	Chn[6].BAddress
		 8	Chn[7].BAddress
		16	Chn[0].TransferBytes		; TransferBytes
		16	Chn[1].TransferBytes
		16	Chn[2].TransferBytes
		16	Chn[3].TransferBytes
		16	Chn[4].TransferBytes
		16	Chn[5].TransferBytes
		16	Chn[6].TransferBytes
		16	Chn[7].TransferBytes
		 1	Chn[0].HDMAIndirectAddressing	; HDMAIndirectAddressing
		 1	Chn[1].HDMAIndirectAddressing
		 1	Chn[2].HDMAIndirectAddressing
		 1	Chn[3].HDMAIndirectAddressing
		 1	Chn[4].HDMAIndirectAddressing
		 1	Chn[5].HDMAIndirectAddressing
		 1	Chn[6].HDMAIndirectAddressing
		 1	Chn[7].HDMAIndirectAddressing
		16	Chn[0].IndirectAddress		; IndirectAddress
		16	Chn[1].IndirectAddress
		16	Chn[2].IndirectAddress
		16	Chn[3].IndirectAddress
		16	Chn[4].IndirectAddress
		16	Chn[5].IndirectAddress
		16	Chn[6].IndirectAddress
		16	Chn[7].IndirectAddress
		 8	Chn[0].IndirectBank		; IndirectBank
		 8	Chn[1].IndirectBank
		 8	Chn[2].IndirectBank
		 8	Chn[3].IndirectBank
		 8	Chn[4].IndirectBank
		 8	Chn[5].IndirectBank
		 8	Chn[6].IndirectBank
		 8	Chn[7].IndirectBank
		 8	Chn[0].Repeat			; Repeat
		 8	Chn[1].Repeat
		 8	Chn[2].Repeat
		 8	Chn[3].Repeat
		 8	Chn[4].Repeat
		 8	Chn[5].Repeat
		 8	Chn[6].Repeat
		 8	Chn[7].Repeat
		 8	Chn[0].LineCount		; LineCount
		 8	Chn[1].LineCount
		 8	Chn[2].LineCount
		 8	Chn[3].LineCount
		 8	Chn[4].LineCount
		 8	Chn[5].LineCount
		 8	Chn[6].LineCount
		 8	Chn[7].LineCount
		 8	Chn[0].FirstLine		; FirstLine
		 8	Chn[1].FirstLine
		 8	Chn[2].FirstLine
		 8	Chn[3].FirstLine
		 8	Chn[4].FirstLine
		 8	Chn[5].FirstLine
		 8	Chn[6].FirstLine
		 8	Chn[7].FirstLine


							; [SPC700 REGISTERS]
		 8	P
		16	YA
		 8	X
		 8	S
		16	PC

							; [APU status]
		32	Cycles
		 1	ShowROM
		 8	Flags
		 8	KeyedChannels
		 8	OutPorts[0]
		 8	OutPorts[1]
		 8	OutPorts[2]
		 8	OutPorts[3]
		16	Timer[0]
		16	Timer[1]
		16	Timer[2]
		16	TimerTarget[0]
		16	TimerTarget[1]
		16	TimerTarget[2]
		 1	TimerEnabled[0]
		 1	TimerEnabled[1]
		 1	TimerEnabled[2]
		 1	TimerValueWritten[0]
		 1	TimerValueWritten[1]
		 1	TimerValueWritten[2]

							; [DSP status]
		16	master_volume_left
		16	master_volume_right
		16	echo_volume_left
		16	echo_volume_right
		32	echo_enable
		32	echo_feedback
		32	echo_ptr
		32	echo_buffer_size
		32	echo_write_enabled
		32	echo_channel_enable
		32	pitch_mod

							; [DSP CHANNEL DATA]
		32	Chn[0].state			; state
		32	Chn[1].state
		32	Chn[2].state
		32	Chn[3].state
		32	Chn[4].state
		32	Chn[5].state
		32	Chn[6].state
		32	Chn[7].state
		32	Chn[0].type			; type
		32	Chn[1].type
		32	Chn[2].type
		32	Chn[3].type
		32	Chn[4].type
		32	Chn[5].type
		32	Chn[6].type
		32	Chn[7].type
		16	Chn[0].volume_left		; volume_left
		16	Chn[1].volume_left
		16	Chn[2].volume_left
		16	Chn[3].volume_left
		16	Chn[4].volume_left
		16	Chn[5].volume_left
		16	Chn[6].volume_left
		16	Chn[7].volume_left
		16	Chn[0].volume_right		; volume_right
		16	Chn[1].volume_right
		16	Chn[2].volume_right
		16	Chn[3].volume_right
		16	Chn[4].volume_right
		16	Chn[5].volume_right
		16	Chn[6].volume_right
		16	Chn[7].volume_right
		32	Chn[0].hertz			; hertz
		32	Chn[1].hertz
		32	Chn[2].hertz
		32	Chn[3].hertz
		32	Chn[4].hertz
		32	Chn[5].hertz
		32	Chn[6].hertz
		32	Chn[7].hertz
		32	Chn[0].count			; count
		32	Chn[1].count
		32	Chn[2].count
		32	Chn[3].count
		32	Chn[4].count
		32	Chn[5].count
		32	Chn[6].count
		32	Chn[7].count
		 1	Chn[0].loop			; loop
		 1	Chn[1].loop
		 1	Chn[2].loop
		 1	Chn[3].loop
		 1	Chn[4].loop
		 1	Chn[5].loop
		 1	Chn[6].loop
		 1	Chn[7].loop
		32	Chn[0].envx			; envx
		32	Chn[1].envx
		32	Chn[2].envx
		32	Chn[3].envx
		32	Chn[4].envx
		32	Chn[5].envx
		32	Chn[6].envx
		32	Chn[7].envx
		16	Chn[0].left_vol_level		; left_vol_level
		16	Chn[1].left_vol_level
		16	Chn[2].left_vol_level
		16	Chn[3].left_vol_level
		16	Chn[4].left_vol_level
		16	Chn[5].left_vol_level
		16	Chn[6].left_vol_level
		16	Chn[7].left_vol_level
		16	Chn[0].right_vol_level		; right_vol_level
		16	Chn[1].right_vol_level
		16	Chn[2].right_vol_level
		16	Chn[3].right_vol_level
		16	Chn[4].right_vol_level
		16	Chn[5].right_vol_level
		16	Chn[6].right_vol_level
		16	Chn[7].right_vol_level
		16	Chn[0].envx_target		; envx_target
		16	Chn[1].envx_target
		16	Chn[2].envx_target
		16	Chn[3].envx_target
		16	Chn[4].envx_target
		16	Chn[5].envx_target
		16	Chn[6].envx_target
		16	Chn[7].envx_target
		32	Chn[0].env_error		; env_error
		32	Chn[1].env_error
		32	Chn[2].env_error
		32	Chn[3].env_error
		32	Chn[4].env_error
		32	Chn[5].env_error
		32	Chn[6].env_error
		32	Chn[7].env_error
		32	Chn[0].erate			; erate
		32	Chn[1].erate
		32	Chn[2].erate
		32	Chn[3].erate
		32	Chn[4].erate
		32	Chn[5].erate
		32	Chn[6].erate
		32	Chn[7].erate
		32	Chn[0].direction		; direction
		32	Chn[1].direction
		32	Chn[2].direction
		32	Chn[3].direction
		32	Chn[4].direction
		32	Chn[5].direction
		32	Chn[6].direction
		32	Chn[7].direction
		32	Chn[0].attack_rate		; attack_rate
		32	Chn[1].attack_rate
		32	Chn[2].attack_rate
		32	Chn[3].attack_rate
		32	Chn[4].attack_rate
		32	Chn[5].attack_rate
		32	Chn[6].attack_rate
		32	Chn[7].attack_rate
		32	Chn[0].decay_rate		; decay_rate
		32	Chn[1].decay_rate
		32	Chn[2].decay_rate
		32	Chn[3].decay_rate
		32	Chn[4].decay_rate
		32	Chn[5].decay_rate
		32	Chn[6].decay_rate
		32	Chn[7].decay_rate
		32	Chn[0].sustain_rate		; sustain_rate
		32	Chn[1].sustain_rate
		32	Chn[2].sustain_rate
		32	Chn[3].sustain_rate
		32	Chn[4].sustain_rate
		32	Chn[5].sustain_rate
		32	Chn[6].sustain_rate
		32	Chn[7].sustain_rate
		32	Chn[0].release_rate		; release_rate
		32	Chn[1].release_rate
		32	Chn[2].release_rate
		32	Chn[3].release_rate
		32	Chn[4].release_rate
		32	Chn[5].release_rate
		32	Chn[6].release_rate
		32	Chn[7].release_rate
		32	Chn[0].sustain_level		; sustain_level
		32	Chn[1].sustain_level
		32	Chn[2].sustain_level
		32	Chn[3].sustain_level
		32	Chn[4].sustain_level
		32	Chn[5].sustain_level
		32	Chn[6].sustain_level
		32	Chn[7].sustain_level
		16	Chn[0].sample			; sample
		16	Chn[1].sample
		16	Chn[2].sample
		16	Chn[3].sample
		16	Chn[4].sample
		16	Chn[5].sample
		16	Chn[6].sample
		16	Chn[7].sample
		16	Chn[0].sample_number		; sample_number
		16	Chn[1].sample_number
		16	Chn[2].sample_number
		16	Chn[3].sample_number
		16	Chn[4].sample_number
		16	Chn[5].sample_number
		16	Chn[6].sample_number
		16	Chn[7].sample_number
		 1	Chn[0].last_block		; last_block
		 1	Chn[1].last_block
		 1	Chn[2].last_block
		 1	Chn[3].last_block
		 1	Chn[4].last_block
		 1	Chn[5].last_block
		 1	Chn[6].last_block
		 1	Chn[7].last_block
		 1	Chn[0].needs_decode		; needs_decode
		 1	Chn[1].needs_decode
		 1	Chn[2].needs_decode
		 1	Chn[3].needs_decode
		 1	Chn[4].needs_decode
		 1	Chn[5].needs_decode
		 1	Chn[6].needs_decode
		 1	Chn[7].needs_decode
		32	Chn[0].block_pointer		; block_pointer
		32	Chn[1].block_pointer
		32	Chn[2].block_pointer
		32	Chn[3].block_pointer
		32	Chn[4].block_pointer
		32	Chn[5].block_pointer
		32	Chn[6].block_pointer
		32	Chn[7].block_pointer
		32	Chn[0].sample_pointer		; sample_pointer
		32	Chn[1].sample_pointer
		32	Chn[2].sample_pointer
		32	Chn[3].sample_pointer
		32	Chn[4].sample_pointer
		32	Chn[5].sample_pointer
		32	Chn[6].sample_pointer
		32	Chn[7].sample_pointer
		32	Chn[0].mode			; mode
		32	Chn[1].mode
		32	Chn[2].mode
		32	Chn[3].mode
		32	Chn[4].mode
		32	Chn[5].mode
		32	Chn[6].mode
		32	Chn[7].mode


							; [SA-1 REGISTERS]
		 8	PB
		 8	DB
		16	P
		16	A
		16	D
		16	S
		16	X
		16	Y
		16	PC

							; [SA-1]
		32	Flags
		 1	NMIActive
		 1	IRQActive
		 1	WaitingForInterrupt
		16	op1
		16	op2
		32	arithmetic_op
		64	sum
		 1	overflow


							; [SPC7110]
		 8	reg4800
		 8	reg4801
		 8	reg4802
		 8	reg4803
		 8	reg4804
		 8	reg4805
		 8	reg4806
		 8	reg4807
		 8	reg4808
		 8	reg4809
		 8	reg480A
		 8	reg480B
		 8	reg480C
		 8	reg4811
		 8	reg4812
		 8	reg4813
		 8	reg4814
		 8	reg4815
		 8	reg4816
		 8	reg4817
		 8	reg4818
		 8	reg4820
		 8	reg4821
		 8	reg4822
		 8	reg4823
		 8	reg4824
		 8	reg4825
		 8	reg4826
		 8	reg4827
		 8	reg4828
		 8	reg4829
		 8	reg482A
		 8	reg482B
		 8	reg482C
		 8	reg482D
		 8	reg482E
		 8	reg482F
		 8	reg4830
		 8	reg4831
		 8	reg4832
		 8	reg4833
		 8	reg4834
		 8	reg4840
		 8	reg4841
		 8	reg4842
		 8	AlignBy
		 8	written
		 8	offset_add
		32	DataRomOffset
		32	DataRomSize
		32	bank50Internal


							; [S7RTC]
		 8	reg[00]
		 8	reg[01]
		 8	reg[02]
		 8	reg[03]
		 8	reg[04]
		 8	reg[05]
		 8	reg[06]
		 8	reg[07]
		 8	reg[08]
		 8	reg[09]
		 8	reg[10]
		 8	reg[11]
		 8	reg[12]
		 8	reg[13]
		 8	reg[14]
		 8	reg[15]
		16	index
		 8	control
		 1	init
		32	last_used



[SSL]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
							; [BPS2]
		 8	BPS2.Version_Minor
		 8	BPS2.Version_Major
		32	BPS2.OS_TimeStamp		; OS specific, following values are for DOS
		 5	BPS2.OS_TimeStamp.Second	; divided by 2
		 6	BPS2.OS_TimeStamp.Minute	; 0..59
		 5	BPS2.OS_TimeStamp.Hour		; 0..23
		 5	BPS2.OS_TimeStamp.Day		; 1..31
		 4	BPS2.OS_TimeStamp.Month		; 1 = Jan, 2 = Feb etc.
		 7	BPS2.OS_TimeStamp.Year		; year minus 1980


							; [SCPU]
		16	CPU.A
		16	CPU.X
		16	CPU.Y
		16	CPU.D
		16	CPU.S
		16	CPU.PC
		 8	CPU.PB
		 8	CPU.DB
		16	CPU.P

		 8	CPU.NMITIMEN
		 8	CPU.WRIO
		 8	CPU.WRMPYA
		 8	CPU.WRMPYB
		16	CPU.WRDIV
		 8	CPU.WRDIVB
		16	CPU.HTIME
		16	CPU.VTIME
		 8	CPU.MDMAEN
		 8	CPU.HDMAEN
		 8	CPU.MEMSEL
		 8	CPU.RDNMI
		 8	CPU.TIMEUP
		 8	CPU.HVBJOY
		 8	CPU.RDIO
		16	CPU.RDDIV
		16	CPU.RDMPY
		16	CPU.JOY1
		16	CPU.JOY2
		16	CPU.JOY3
		16	CPU.JOY4


							; [SPPU]
		 8	PPU.INIDISP
		 8	PPU.OBJSEL
		 8	PPU.OAMADDL
		 8	PPU.OAMADDH
		 8	PPU.BGMODE
		 8	PPU.MOSAIC
		 8	PPU.BG1SC
		 8	PPU.BG2SC
		 8	PPU.BG3SC
		 8	PPU.BG4SC
		 8	PPU.BG12NBA
		 8	PPU.BG34NBA
		16	PPU.BG1HOFS
		16	PPU.BG1VOFS
		16	PPU.BG2HOFS
		16	PPU.BG2VOFS
		16	PPU.BG3HOFS
		16	PPU.BG3VOFS
		16	PPU.BG4HOFS
		16	PPU.BG4VOFS
		 8	PPU.VMAINC
		 8	PPU.VMADDL
		 8	PPU.VMADDH
		 8	PPU.M7SEL
		16	PPU.M7A
		16	PPU.M7B
		16	PPU.M7C
		16	PPU.M7D
		16	PPU.M7X
		16	PPU.M7Y
		 8	PPU.CGADD
		 8	PPU.W12SEL
		 8	PPU.W34SEL
		 8	PPU.WOBJSEL
		 8	PPU.WH0
		 8	PPU.WH1
		 8	PPU.WH2
		 8	PPU.WH3
		 8	PPU.WBGLOG
		 8	PPU.WOBJLOG
		 8	PPU.TM
		 8	PPU.TS
		 8	PPU.TMW
		 8	PPU.TSW
		 8	PPU.CGWSEL
		 8	PPU.CGADSUB
		16	PPU.COLDATA
		 8	PPU.SETINI
		 8	PPU.MPYL
		 8	PPU.MPYM
		 8	PPU.MPYH
		16	PPU.OPHCT
		16	PPU.OPVCT
		 8	PPU.STAT77
		 8	PPU.STAT78


							; [SAPU]
		 8	APU.A
		 8	APU.X
		 8	APU.Y
		 8	APU.SP
		16	APU.PC
		 8	APU.P

		 8	APU.APUIO0
		 8	APU.APUIO1
		 8	APU.APUIO2
		 8	APU.APUIO3


							; [SAS1]
		16	SAS.A
		16	SAS.X
		16	SAS.Y
		16	SAS.D
		16	SAS.S
		16	SAS.PC
		 8	SAS.PB
		 8	SAS.DB
		16	SAS.P

		 8	SAS.SFR
		 8	SAS.CFR
		16	SAS.HCR
		16	SAS.VCR
		 8	SAS.MR0
		 8	SAS.MR1
		 8	SAS.MR2
		 8	SAS.MR3
		 8	SAS.MR4
		 8	SAS.OF
		16	SAS.VDP
		 8	SAS.VC

		 8	SAS.CCNT
		 8	SAS.SIE
		 8	SAS.SIC
		16	SAS.CRV
		16	SAS.CNV
		16	SAS.CIV
		 8	SAS.SCNT
		 8	SAS.CIE
		 8	SAS.CIC
		16	SAS.SNV
		16	SAS.SIV
		 8	SAS.TMC
		 8	SAS.CTR
		16	SAS.HCNT
		16	SAS.VCNT
		 8	SAS.CXB
		 8	SAS.DXB
		 8	SAS.EXB
		 8	SAS.FXB
		 8	SAS.BMAPS
		 8	SAS.BMAP
		 8	SAS.SBWE
		 8	SAS.CBWE
		 8	SAS.BWPA
		 8	SAS.SIWP
		 8	SAS.CIWP
		 8	SAS.DCNT
		 8	SAS.CDMA
		 8	SAS.SDA[0]
		 8	SAS.SDA[1]
		 8	SAS.SDA[2]
		 8	SAS.DDA[0]
		 8	SAS.DDA[1]
		 8	SAS.DDA[2]
		16	SAS.DTC
		 8	SAS.BBF
		 8	SAS.BRF0
		 8	SAS.BRF1
		 8	SAS.BRF2
		 8	SAS.BRF3
		 8	SAS.BRF4
		 8	SAS.BRF5
		 8	SAS.BRF6
		 8	SAS.BRF7
		 8	SAS.BRF8
		 8	SAS.BRF9
		 8	SAS.BRFA
		 8	SAS.BRFB
		 8	SAS.BRFC
		 8	SAS.BRFD
		 8	SAS.BRFE
		 8	SAS.BRFF
		 8	SAS.MCNT
		16	SAS.MA
		16	SAS.MB
		 8	SAS.VBD



[SceneViewer HDMA info rows]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
enabled
direction

HDMA table
addressing
indirect bank
destination

transfer mode
bytes
registers
transfer order



[SceneViewer info rows]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
{LV_InfoScreen}
BG mode
BG3 (priority 1) on top
brightness
color constant
color window
color window
beam position
beam counter
EXTBG
forced blanking
H-512 mode
interlace
internal screen size
mosaic size
overscan (239 lines)
PAL mode
range over
time over
window 1 horz. borders
window 2 horz. borders

{LV_InfoOBJ}
enabled on main
enabled on sub
FirstSprite
single lines in interlace
tile base 1
tile base 2
sprite size 1 (small)
sprite size 2 (large)

{LV_InfoBGs}
bits per pixel
enabled: main
enabled: sub
mosaic
horz. position
vert. position
size
tile base
tile size
tilemap base
tilemap size

{LV_InfoWnds}
enabled
inversed
on main
on sub
1-2 logic

{LV_InfoM7}
A
B
C
D
center
position
flip
repeating tilemap
rest filled by tile 0

{LV_InfoMath}
mainscreen ...
on BG1 pixels
on BG2 pixels
on BG3 pixels
on BG4 pixels
on OBJ pixels
on BACK pixels
half result
direct color mode


[Form_Cart ComboBox info]  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
{ComboBox_ExpRAM}
00h = none
01h = 0016 Kbits or less
03h = 0064 Kbits or less
05h = 0256 KBits or less
06h = 0512 KBits or less
07h = 1024 KBits or less

{ComboBox_MapMode}
20h = Mode 20 = SlowROM (200ns)
21h = Mode 21 = SlowROM (200ns)
22h = reserved
23h = Mode 23 = SlowROM (200ns) (SA-1)
25h = Mode 25 = SlowROM (200ns)
30h = Mode 20 = FastROM (120ns)
31h = Mode 21 = FastROM (120ns)
35h = Mode 25 = FastROM (120ns)

{ComboBox_CoCPU}
00h = none or DSP
01h = Super FX
02h = OBC1
03h = SA-1
0Eh = other
0Fh = custom chip

{ComboBox_RomSize}
08h = 02 Mbits
09h = 04 Mbits or less
0Ah = 08 Mbits or less
0Bh = 16 Mbits or less
0Ch = 32 Mbits or less
0Dh = 64 Mbits or less

{ComboBox_SRAM}
00h = none
01h = 0016 Kbits
02h = 0032 Kbits
03h = 0064 Kbits
04h = 0128 Kbits
05h = 0256 Kbits
06h = 0512 Kbits
07h = 1024 Kbits

{ComboBox_Region}
00h = Japan
01h = North America
02h = Europe
03h = Scandinavia
04h = Finland
05h = Denmark
06h = France
07h = Dutch
08h = Spain
09h = Germany, Swiss, Austria
0Ah = Italy
0Bh = Hong Kong, China
0Ch = Indonesia
0Dh = Korea
0Eh = Common
0Fh = Canada
10h = Brazil
11h = Australia
12h = other variation
13h = other variation
14h = other variation

{ComboBox_License}
00h
01h = Nintendo
02h
03h = Imagineer-Zoom
04h
05h = Zamuse
06h = Falcom
07h
08h = Capcom
09h = HOT-B
0Ah = Jaleco
0Bh = Coconuts
0Ch = Rage Software
0Dh
0Eh = Technos
0Fh = Mebio Software
10h
11h
12h = Gremlin Graphics
13h = Electronic Arts
14h
15h = COBRA Team
16h = Human/Field
17h = KOEI
18h = Hudson Soft
19h
1Ah = Yanoman
1Bh
1Ch = Tecmo
1Dh
1Eh = Open System
1Fh = Virgin Games
20h = KSS
21h = Sunsoft
22h = POW
23h = Micro World
24h
25h
26h = Enix
27h = Loriciel/Electro Brain
28h = Kemco
29h = Seta Co.,Ltd.
2Ah
2Bh
2Ch
2Dh = Visit Co.,Ltd.
2Eh
2Fh
30h
31h = Carrozzeria
32h = Dynamic
33h = [extended header?]
34h = Magifact
35h = Hect
36h
37h
38h
39h
3Ah
3Bh
3Ch = Empire Software
3Dh = Loriciel
3Eh
3Fh
40h = Seika Corp.
41h = UBI Soft
42h
43h
44h
45h
46h = System 3
47h = Spectrum Holobyte
48h
49h = Irem
4Ah
4Bh = Raya Systems/Sculptured Software
4Ch = Renovation Products
4Dh = Malibu Games/Black Pearl
4Eh
4Fh = U.S. Gold
50h = Absolute Entertainment
51h = Acclaim
52h = Activision
53h = American Sammy
54h = GameTek
55h = Hi Tech Expressions
56h = LJN Toys
57h
58h
59h
5Ah = Mindscape
5Bh
5Ch
5Dh = Tradewest
5Eh
5Fh = American Softworks Corp.
60h = Titus
61h = Virgin Interactive Entertainment
62h = Maxis
63h
64h
65h
66h
67h = Ocean
68h
69h = Electronic Arts
6Ah
6Bh = Laser Beam
6Ch
6Dh
6Eh = Elite
6Fh = Electro Brain
70h = Infogrames
71h = Interplay
72h = LucasArts
73h = Parker Brothers
74h
75h = STORM
76h
77h
78h = THQ Software
79h = Accolade Inc.
7Ah = Triffix Entertainment
7Bh
7Ch = Microprose
7Dh
7Eh
7Fh = Kemco
80h = Misawa
81h = Teichio
82h = Namco Ltd.
83h = Lozc
84h = Koei
85h
86h = Tokuma Shoten Intermedia
87h
88h = DATAM-Polystar
89h
8Ah
8Bh = Bullet-Proof Software
8Ch = Vic Tokai
8Dh
8Eh = Character Soft
8Fh = I''Max
90h = Takara
91h = CHUN Soft
92h = Video System Co., Ltd.
93h = BEC
94h
95h = Varie
96h
97h = Kaneco
98h
99h = Pack in Video
9Ah = Nichibutsu
9Bh = TECMO
9Ch = Imagineer Co.
9Dh
9Eh
9Fh
A0h = Telenet
A1h
A2h
A3h
A4h = Konami
A5h = K.Amusement Leasing Co.
A6h
A7h = Takara
A8h
A9h = Technos Jap.
AAh = JVC
ABh
ACh = Toei Animation
ADh = Toho
AEh
AFh = Namco Ltd.
B0h
B1h = ASCII Co. Activison
B2h = BanDai America
B3h
B4h = Enix
B5h
B6h = Halken
B7h
B8h
B9h
BAh = Culture Brain
BBh = Sunsoft
BCh = Toshiba EMI
BDh = Sony Imagesoft
BEh
BFh = Sammy
C0h = Taito
C1h
C2h = Kemco
C3h = Square
C4h = Tokuma Soft
C5h = Data East
C6h = Tonkin House
C7h
C8h = KOEI
C9h
CAh = Konami USA
CBh = NTVIC
CCh
CDh = Meldac
CEh = Pony Canyon
CFh = Sotsu Agency/Sunrise
D0h = Disco/Taito
D1h = Sofel
D2h = Quest Corp.
D3h = Sigma
D4h
D5h
D6h = Naxat
D7h
D8h = Capcom Co., Ltd.
D9h = Banpresto
DAh = Tomy
DBh = Acclaim
DCh
DDh = NCS
DEh = Human Entertainment
DFh = Altron
E0h = Jaleco
E1h
E2h = Yutaka
E3h
E4h = T&ESoft
E5h = EPOCH Co.,Ltd.
E6h
E7h = Athena
E8h = Asmik
E9h = Natsume
EAh = King Records
EBh = Atlus
ECh = Sony Music Entertainment
EDh
EEh = IGS
EFh
F0h
F1h = Motown Software
F2h = Left Field Entertainment
F3h = Beam Software
F4h = Tec Magik
F5h
F6h
F7h
F8h
F9h = Cybersoft
FAh
FBh
FCh
FDh
FEh
FFh = Hudson Soft
